Franson SerialTools RunTime is a free addin for SerialTools.SerialTools is the easiest way to include serial port support in your application!Many samples, easy guides to get started and a very straight forward API makes SerialTools simple to use even for a novice programmer. For the more advanced developer all features are in place for complete control of the serial port.
Franson Serial Tools 64 Bit
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Windows 11 update loaded Prolific PL2303 driver 3.8.40.0 and when I go to device manager it says "Please install corresponding PL2303 driver to support Windows 11 and further OS" This driver does not even attempt to communicate with my X10 CM11 hooked to my serial port. I had to go to Prolific website and load their current driver 3.6.81.357. (uninstall driver first) Serial to X10 device now working fine. Don't install Windows update for Prolific or it will change it back.
This is a simple receiver that is to be connected to any computer. Delivered with a driver for most recent Windows. To make it run under Linux, just compile your kernel with support for pl2303 serial-to-usb (as a module or into kernel), then everything should be fine with GPSd.
The unit is solid, well constructed and quite compact. It is waterproof (useful if it rains, or for other forms of wet mapping) It contains a non-replaceable rechargeable li-ion batteries with a maximum battery life of 32 hours. The standard version comes with a car charger as standard. Both models have a USB serial connection for upload and recharging. The ability to recharge via the USB cable is a very nice feature. It also comes with a standard adaptor for recharging from a car and the most compact and nifty 240 volt mains adaptor I have ever seen.
It comes with a simple Windows application for uploading/downloading routes, waypoints and trackpoints. Installation of the USB serial driver was a bit fiddly, but otherwise it works fine. In the software "Version 1.1 B20060228" there are two main download options (Oziexplorer/GPX/CSV and Waypoint+) in addition to the raw NMEA files. This software version also uses GPSBabel to export the data in KML format suitable for use with Google Maps and Google Earth. There is a backup/restore function which creates a 512k binary file which I suppose is a dump of its flash memory.
For Linux users, the Windows application appears to work OK using wine. The USB interface on the device is supported by the pl2303 driver and appears as a serial port (e.g. /dev/ttyUSB0) providing raw NMEA data for gpsd or gpsdrive. Some further Linux information is at NaviLink for Linux. This page includes a link to a page describing a Perl script that can be used in place of the Windows program provided with the device.
First you need to load two modules, usbserial and cp2101 which are included in kernel 2.6.20 (probably earlier versions too, didn't check it). If the device gets plugged you'll get a device like /dev/ttyUSB0 to access your device (don't forget to give yourself permissions accordingly). The device has to be in LOG mode. It gets recognized in the other modes too, but didn't work! In case you use gpsd use
The major functional portions of the PCB pair are shown in Fig. 1.Each PCB contains a field programmable gate array (FPGA) chip and a pair ofserializer/deserializer (SerDes) chips. Each SerDes can support up to fourbi-directional Gigabit channels. The FPGA exchanges 10-bit parallel data withthe SerDes at 125 MHz. The SerDes converts between 10-bit parallel data at125 MHz and serial data at 1.25 GHz. For synchronous communication on theclassical channel, no additional support is needed. Synchronous communicationrequires data to be sent continuously so that the receiver can recover thetransmit clock and use it to correctly extract the bits of the data stream.When there is no real data to send, predefine idle characters are sent tofill any potential absence of data. Clock recovery is an important aspect ofsynchronous communication because although the transmitter and receiver usesimilar clocks (oscillators), the clocks are not exactly the same. If aninexact clock were used to extract bits from the data stream it would resultin errors. For example a typical 125 MHz oscillator has a precision of about[10.sup.-5], which is +/-1,250 Hz from the rated frequency. This could resultin a difference of up to 2,500 clocks per second between the transmitter andreceiver.
We treat each random, relatively slow detector signal as a highspeed serial data stream on a separate quantum channel. The serial data ratedetermines the time bin resolution of our detection events. The data in eachquantum channel is unsynchronized, sparse and random. A SerDes requires acontinuous, synchronized data stream since one of its functions is to recoverthe clock of the received data stream. To alleviate this problem we developedspecial circuitry to condition and prepare the quantum data for processing bythe SerDes. As the quantum signals arrive at Bob's PCB, their phase(sub-bit timing) is aligned by a programmable delay chip to a GHz clockdriving a pair of flip-flops. That GHz clock is the recovered clock from thereceived classical channel and is identical to the transmission clock.Because of jitter, the quantum signals are not stable and so we useflip-flops to stabilize them. The stable flip-flop output is re-aligned withthe replicated classical channel data stream by a second programmable delaychip and then XORed with the replicated classical serial data stream and sentto the SerDes as a synchronous signal. This XOR process"piggybacks" the sparse quantum data stream onto a well-formedsynchronous data stream that can now be processed by the SerDes. Onceprocessed by the SerDes, the parallel data is passed to the FPGA where it isagain XORed with the now parallel classical data stream, leaving the originalsparse quantum data stream. This dual XOR process to piggyback the sparsequantum stream onto the classical data stream and then remove the classicaldata is necessary since the FPGA is not fast enough to directly samplesignals at GHz rates. Once the sparse quantum stream is inside the FPGA, wecan search it in parallel for a "0" to "1" transitionthat designates a photon detection event. Its bit position is the time bin inwhich it occurs. Part of the startup configuration procedure involvesaligning the quantum channels with the classical channel. This determinessub-bit time settings of the delay chips and a multiple-bit time delaysetting within the FPGA. 2ff7e9595c
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